(This information is from Nimai Malle<email@example.com>)
The PC-Engine can only display one background at a time. The background is made up of definable characters all 8x8 pixels in size. The actual size of the BG can be much larger than the display area of the TV screen, allowing scrolling, etc. As with sprites, there is also a set of 16 palettes, each with 16 colours for use with BG characters. Each character can use it's own palette from those 16. Which area of the BG is currently displayed on the screen is determined by scroll registers within the PC-Engine, with (0,0) being the upper left hand corner. By writing new values to these registers, the area being displayed is "instantly" changed. To scroll, just increment this register either in the X or Y direction.
The TG-16 has 512 colours. Some colours are necessarily duplicated.
The PC-Engine and Duo machines do display 16 colours out of a possible 512 per sprite. There are 16 palettes, each holding 16 colours. A single sprite can use one of those 16 palettes. Therefore, one sprite may use one set of 16 colours, and another a different set, hiding the limitations of the 16 colour limit. Also a sprite is 16x16 dots in size, so most object are comprised of a set of sprites.
In the BG, colour 0 of all palettes are equal. Colour 0 of palette 0 determines colour 0 of all the BG palettes. Even though these colour CAN be set independently, the screen will not reflect these settings.In the Sprites colours, colour 0 is transparent in all palettes, although it does peek it's head in a peculiar place; beyond the display width of the BG. Explanation: The BG display area (in it's most often used setting) is 256x216 The display width of a television may be adjusted to squash the screen vertically, or horizontally. Even normal TVs show a little more that 256 TG-16 dots wide, leaving a black border on the sides. This border colour is actually controlled by sprite colour 0. The programmer can actually set the screen width more narrow or vertically shorter, showing more of this area. It's only use that I've ever implemented was in measuring the CPU load of the TG-16 during development.
NEC doesn't sanction weird resolutions. As far as I know, there is no setting that allows more that 256 dots vertically, but I have written games using 512x256. Colours are DEFINITELY fixed at 512 (minus duplicates) but when in 512x256 mode, dithering colours, or displaying alternating vertical bands of, say blue and red, give a convincing display of purple, so more colours can be SHOWN this way, but still not true colour.
As for TurboExpress compatibility, I think it can handle the 320x256 mode used in Y's and others, but I've never tested 512x256... Interesting! SuperGrafx is a strange beast. It has the same CPU as the TG-16, but with two sets of graphic control chips. This means hex $20000 bytes of VRAM, two BGs twice as many sprites (making 128). BUT this meant more work for that little CPU. This was the complaint of most developers. Needless to say, the system didn't catch on, although *I* think it's games were GREAT!
There are 3 memory locations involved, all in segment $FF (hardware I/O segment). The CPU provides 3 functions, to directly access this registers: ST0, ST1 and ST2.
|$0000||(W)||VDC register select|
|$0000||(R)||VDC status register|
|$0002||(R/W)||LSB of Data value|
|$0003||(R/W)||MSB of Data value|
The VDC status register:
|0||MAWR||Memory Address Write Register|
|1||MARR||Memory Address Read Register|
|2||VRR||VRAM Read Register|
|2||VWR||VRAM Write Register|
|6||RCR||Raster Counter Register|
|7||BXR||Background X-Scroll Register|
|8||BYR||Background Y-Scroll Register|
|9||MWR||Memory-access Width Register|
|10||HSR||Horizontal Sync Register (?)|
|11||HDR||Horizontal Display Register (?)|
|15||DCR||(DMA) Control Register|
|16||SOUR||(DMA) Source Register|
|17||DESR||(DMA) Destination Register|
|18||LENR||(DMA) Length Register|
|19||SATB||Sprite Attribute Table|
The VRR register is the only one VDC register that can be read and written. It reads the value from VRAM at the address specified by the MARR. When the value is read from the second byte-port at$0003, the MARR register (i.e. the address to read from) is auto-incremented.
When writing data into this register, it is written to VRAM at the address specified by the MAWR. When the value is written to the second byte-port at $0003, the MAWR register (i.e. the address to write to) is auto-incremented. The amount of incrementation is selected by CR.
The Control Register controls several parameters of display generation. The IW bits control the auto-incrementation of the MAWR register.
The rcr bit controls the generation of a raster counter IRQ. The VDC generates an IRQ, when the scanline specified in the RCR register is displayed. You need to add 64 to the RCR register to get the correct scanline.
The pattern-map is at the beginning of the VRAM. It can be 32, 64 or 128 cells wide and 32 or 64 cells high. The lower 12 Bits of each entry point to the pattern-data, the higher 4 bits indicate the palette.
Every pattern is 8x8 Pixel. Plane one and two is at current word, plane three and four are at current word+8.
The HSR, VDC, VPR, VDW and VCR registers control several aspects of the generation of the video signal. The only known register, yet, is the lower half of HDR. It controls the horizontal width of display generation. The value in this register is the number of horizontal tiles minus one. Normal values are 31, for 32 tiles and 256 pixel horizontally, 39, for 40 tiles or 320 pixel and 63, for 64 tiles or 512 pixel.
Scrolling is done with the BXR and BYR registers. Writing to this registers immediately causes the background to scroll. You can reload these registers during an RCR interrupt to create a split-screen.
These registers control directly the x and y offset of the generated display. It looks like you have to reset BYR during a VBL IRQ to get a correct display.
The size of the virtual screen is controlled by the MWR register. To get correct scrolling you have to set the virtual map bigger than the physical display.
The DCR, SOUR, DESR and LENR registers control DMA operations. The DMA operation starts, as soon as the length is written into the LENR register.
The only thing I know is, that the flags of DCR correspond to the status-register. But I don't know, how.
The SATR register points to a table with 64 entries, for every sprite one. The basic unit of a sprite is a cell; cells are 16x16. One plane (all 16 bits horizontally) is at current word; the next plane is at current word+16, the third and fourth planes being at current word+32 and current word+48.
You have got to shift the pattern address left 5 bits, and then it's an pointer into the VRAM. The pattern data for a 1-cell wide sprite must be aligned like the pattern data for a 2-cell wide sprite.
The sprite attributes control, how a sprite is displayed. A sprite can be mirrored, and you can make sprites from 16 x 16 pixel to 32 x 64 pixel.
A sprite is always aligned like 32 pixel wide sprite. That means that a 16 pixel wide sprite is interleaved with another sprite.
|0||'y' position (bottom 10 bits only)|
|1||'x' position (bottom 10 bits only)|
|2||pattern address (bottom 11 bits only).|
|$0400||write$00 to reset|
|$0402||LSB of byte offset into palette|
|$0403||MSB of byte offset into palette|
|$0404||LSB of 16-bit palette data|
|$0405||MSB of 16-bit palette data|
The DAC has a palette of 512 colours. The bitmap of the palette data is this: 0000000gggrrrbbb. That means, that you have a range from 0-7 for every colour, resulting in a total number of 512 colours (8 * 8 * 8). You can read and write the DAC-registers.